Title: Performance Analysis and Propagation Delay Time Estimation of Logic Families with HBTs
Authors: J. del Pino, A. Hernández, B. González, J. García, y A. Nunez.
Conference name: XII Design of Circuits and Integrated Systems Conference
A study of the operation and performance of ECL and CML families implemented with HBTs has been carried out. We have analyzed, by simulation, the beliaviour of both logic families and compared (heir performances with other high-speed FET based families. As in silicon BJT-based circuits compared with CMOS, the IIHT-based families are faster hot more power is consumed with regard to the other FET families. We have also developed tuning models expressed with simple equations. These equations are technology dependent and predict the timing operation of logic circuits as function of load capacitances and of fan-mil. It tits well the behaviour of the gates against IISPICL simulations with errors smaller than 4% in all studied cases.