Title: Area Efficient Dual-Fed CMOS Distributed Power Amplifier
Authors: Javier del Pino, Sunil L. Khemchandani, Sergio Mateos-Angulo, Daniel Mayor-Duarte and Mario San-Miguel-Montesdeoca
Journal name: Electronics
Abstract: In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases.