Title: An Ouput Capacitorless Low Dropout Voltage Regulator with a Novel Fast Settling Path
Authors: J.M Hinojo, C. Lujan-Martinez, A. Torralba, J. Ramirez-Angulo, G. Bistue, J. del Pino
Journal name: XXIX Design of Circuits and Integrated Systems Conference (DCIS)
Abstract: In this paper an output-capacitorless Low Drop-Out (LDO) regulator based on the Folded Flipped Voltage Follower (FFVF) with a fast path to improve the transient response and the settling time is described. A fast settling path has been added to discharge rapidly the parasitic capacitance of the pass transistor gate. This regulator has been designed in a standard 65 nm CMOS technology. Post-layout simulation results show a load and a line regulation of 100.3 μV/mA and 37.3 mV/V, respectively. Furthermore, the output voltage peaks are kept under 160 mV for 0.1-100 mA load variation with a rise and fall time of 100 ns. Finally, this regulator has a quiescent current consumption as low as 13.66 μA.